L. Virtanen and J. Nieminen, “Simulation-Driven Multi-Kernel FPGA Dataflow Optimization for Low-Latency and Resource-Efficient Digital Signal Processing Pipelines”, IAJSE, vol. 12, no. 4, pp. 157–165, Dec. 2025, doi: 10.71086/IAJSE/V12I4/IAJSE1285.