Thermal- and Workload-Aware Reconfigurable VLSI Accelerator Modeling for Edge-AI Signal Processing

Abstract

Edge AI systems, followed by hardware accelerators of specialized hardware are becoming increasingly dependent on computationally-intensive signal-processing and machine-learning workloads, with severe latency and power requirements. Conventional processor-based architectures are not able to deliver adequate throughput in addition to energy efficiency in relation to real time inference. Reconfigurable VLSI accelerators have become a potential alternative as they allow data paths to be customized to exploit massive parallelism. Nevertheless, the design of such accelerators should be performed with the consideration of the thermal behaviour, the diversity of workloads, and resources. Most current hardware accelerators are specialized to a particular workload, e.g. convolutions, making them less flexible to use in heterogeneous edge computing systems. The work describes a simulation-based platform of modelling thermal- and workload-aware reconfigurable VLSI accelerators, based on edge-AI signal processing activity. The suggested architecture constitutes signal processing kernels in the form of modular accelerator blocks linked via a dynamically reconfigurable dataflow network. To test the architecture at different levels of computational intensities, synthetic workloads that model audio, radar, and image signal processing loads are generated. The mechanisms of thermal-aware scheduling and adaptive resource allocation are proposed to reduce overheating and enhance the energy efficiency. Through experimental assessment through architectural simulation, the architectural accelerator architecture has shown a lot of enhancement in processing throughput at stable thermal behaviour under heavy workloads. The results show that a combination of thermal awareness and workload adaptivity is critical in the future design of an edge-AI hardware.