Simulation-Driven Multi-Kernel FPGA Dataflow Optimization for Low-Latency and Resource-Efficient Digital Signal Processing Pipelines

Abstract

Hardware acceleration in digital signal processing (DSP) applications required by edge computing, wireless communication, and multimedia analytics is becoming more and more apparent because of the high throughput needed and the low latency as well as resource usage required. FPGAs have provided a desirable platform to do such applications due to their reconfigurable architecture and capability of executing highly parallel processing pipelines. Most current DSP accelerators are however designed to optimise a single algorithm e.g. the fast fourier transform or filtering operations and hence not very flexible and therefore do not efficiently utilize resources when more than one kernel needs to be run in the same pipeline. In this paper, a multi-kernel FPGA dataflow optimization framework is suggested based on simulation and modelling a number of DSP kernels within one hardware pipeline. The methodology is an integration of dataflow graph modelling, latency-sensitive scheduling and resource sharing techniques with the aim of maximising the throughput and computational efficiency. The signal workload generator is a synthetic workload generator that mimics various conditions of the application and therefore makes it possible to evaluate the application without real-time data. Hardware simulation and estimation with synthesis are used to measure the latency, throughput, power consumption and the use of FPGA resources by the architecture. It was found that the presented multi-kernel pipeline architecture is much more efficient in terms of utilising pipelines and ranges of processing latency as compared to the traditional single-kernel accelerators. The results indicate that architectural exploration can offer a feasible approach to the development of scalable DSP accelerators applicable in edge computing and communication systems through simulation-based exploration.