Design of Two New High-Performance Full Adders in Sub-threshold Region for Ultra-Low Power Applications

Authors

  • Ebrahim Pakniyat
  • Seyyed Reza Talebiyan
  • Milad Jalalian Abbasi Morad
  • Farnaz Loghmani

Keywords:

1-bit adder, sub-threshold voltage technology, propagation delay, power consumption, high performance

Abstract

This paper presents two new structures of 1-bit full adder. It compares full adder sub-circuits and two proposed full adder circuits with common circuits in terms of propagation delay, power consumption, power delay product and square power delay product in sub-threshold voltage technology. HSPICE simulations show that all the proposed adders are improved significantly in power delay product and square power delay product parameters. The full adder structures are compared in 260 (mV) supply voltage

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Published

2015-12-30

Issue

Vol. 2 No. 2 (2015)

Section

Articles

How to Cite

Pakniyat, E., Talebiyan, S. R., Morad, M. J. A., & Loghmani, F. (2015). Design of Two New High-Performance Full Adders in Sub-threshold Region for Ultra-Low Power Applications. International Academic Journal of Science and Engineering, 2(2), 73-82. https://iaiest.com/iaj/index.php/IAJSE/article/view/1300